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Vias is the important constitute of PCB, the cost of drilling fee is 30%-40% of whole PCB cost.

• Parasitic capacity of vias

The parasitic capacity exists in vias refer to ground layer. Assume ground layer isolate via diameter is D2, via pad diameter is D1, PCB thickness is T, dielectric constant is ε, then vias parasitic capacity is: C=1.41ε TD1/(D2-D1) ,Vias parasitic impact the time of transmission up., slow the speed of circuit.E.g. PCB with 50mil thickness,if the via diameter is 10mil and pad diameter is 20mil,The distance between pad and ground copper is 32mil, then we can calculates parasitic capacity is: C=1.41×4.4×0.050×0.020/(0.032-0.020)=0.517pf, the time change of parasitic capacity is: T10-90=2.2C(Z0/2)=2X0.517X(55/2)=31.28ps. From the data we can see one single via is not big impact for transmission. But if there have many vias in board, the impact is huge,so design enginner should be consider this situation.

•  Parasitic inductance of vias

The parasitic inductance is also exists in vias,in high-speed circuit design,the endanger of parasitic inductance is more than parasitic capacity.its parasitic serics inductance will down shunt capacity contribution,weaken filter action of whole power system. We can calculate a vias parasitic inductance use the formula: L=5.08h｛In(4h/d)+1｝,L is the inductance,h is the vias length,d is the via diameter.we can see the via’s diameter is small impact for the inductance in the formula. The via’s length is big impact for the inductance. We calculate via’s inductance follow above data: L=5.08×0.050｛In(4×0.050/0.010)+1｝=1.015nH. If the signal time is 1ns,then impedance is:XL=πL/T10-90=3.19Ω, such impedance can’t be ignore in high speed circuit.Especially there need two vias for one shunt capacity,so the parasitic inductance will fold increase.

•  Vias layout in high-speed PCB

After above analysed,we can see vias will bring negative impacts in high-speed circuit design. We can follow below rules for avoid the via’s negative impacts.

(a. ) Consider from cost and signal quality, choose suitable via size. It’s better set 10/20mil of drill/pad for 6~10 Layer PCB. For high density and small dimension,also can try 8/18mil vias.it can be considered large vias for power and ground trace to reduce impedance.

(b. ) From above two formulas,we can see thin PCB in favor of reduce parasitic capacity and inductance.

(c. ) Vias near power and ground components is as close as possible to components,the same time power and ground trace try get short and large to reduce impedance.

(d. ) Signal trace don’t change layer if unnecessary,means don’t set redundant vias.

(e. ) Set some vias near the vias of signal trace so that it can provide return circuit for signal. More vias can be set in ground layer. Above vias module we discussed under exist pad in every layer. Sometimes, we can decrease the pads size or delete them.Especially under vias density is big, it may lead to break slot of break return circuit in copper layer. We need decrease the pad size of these vias or move vias position to solve the question.

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