For the selection of PCB sheets, a balance point must be reached between the design requirements and the mass production as well as the cost. Design requirements include electrical and mechanical components of the two parts. This material problem is important when designing a very high speed PCB board (greater than the frequency of GHz). For example, in today’s commonly used FR-4 materials, the dielectric loss at several GHz frequencies can have a significant effect on signal attenuation and may not be applicable. For electrical purposes, however, it should be noted whether the dielectric constant and the dielectric loss are applicable at the designed frequency.

How to avoid high frequency interference?

The basic idea of avoiding high frequency interference is to minimize the interference of high frequency signals and electromagnetic fields, also called crosstalk). The distance between the high speed signal and the analog signal can be used, or the ground guard/shunt traces is next to the analog signal. Attention must also be paid to the noise interference of the analog ground digitally.

In high-speed design, how to solve the integrity of the signal?

Signal integrity is essentially a problem of impedance matching. The factors that affect impedance matching include the signal source architecture and output impedance , the characteristic impedance of the line, the characteristics of the load, the topology of the routing architecture, etc.. The solution is based on the topology of the termination and the adjustment line.

How is the differential distribution pattern implemented?

Differential pair wiring has two points to note, one is the length of the two lines to be as long as possible, and the spacing of the two lines (where the distance is determined by differential impedance) to remain the same, that is, to keep parallel. There are two parallel ways, one is the two lines walking on the same line (side-by-side), and the other is the two lines moving up and down the next two layers (over-under). In general, side-by-side implemented more.

For a clock signal line with only one output, what is the difference between the lines?

In order to use differential distribution lines, it must be the signal source and the receiver that are differential signals. It is impossible for a clock signal with only one output to use differential distribution lines.

Can a matching resistor be added between the differential lines of the receiver?

The matching resistance between the differential lines of the receiving end is usually added, and the value should be equal to the value of the differential impedance. The quality of the signal will be better.

Why should differential pair routing be near and parallel?

The routing of the differential pair is appropriate to be near and parallel. The proper spacing is close to that because this will affect the differential impedance value, and this value is an important parameter to the design differential impedance. Parallel is also necessary to maintain consistency of differential impedances. If the two lines are routed suddenly near suddenly far, the differential impedance will be inconsistent, which will affect signal integrity and time delay.

How to deal with some theoretical conflicts in actual wiring?

Basically, the separation of modules / numbers is correct. It should be noted that the signal should not be crossed as far as possible in the moat, and do not let the returning current path become too large.The crystal is a positive feedback oscillation circuit simulation, have stable oscillation signal, gain and loop must meet the phase specification, and the specification of this oscillation analog signal is vulnerable to interference, even with the ground guard traces may not be completely isolated interference. And too far away, the noise on the ground plane will also affect the positive feedback oscillation circuit. So make sure that the distance between the crystal and the chip is near.Indeed, there are many conflicts between high-speed wiring and EMI requirements. But the basic principle is that, because of the resistor, capacitor or ferrite bead added by EMI, some electrical characteristics of the signal can not be met. Therefore, it is better to solve the problem of EMI by arranging the routing and PCB stacking techniques, such as high-speed signals coming in the inner layer. Finally, resistors, capacitors, or ferrite bead are used to reduce the damage to the signal.

How to solve the contradiction between manual routing and automatic routing of high speed signals?

At present, most of the automatic cabling devices with strong cabling software have set constraints to control the winding mode and the number of vias. Each EDA company’s winding engine capabilities and constraints setting projects sometimes are great different.

Regarding test coupon

The test coupon is used to measure whether the characteristic impedance of the PCB plate produced by TDR (Time, Domain, Reflectometer) meets the design requirements. Generally, the impedance to be controlled has a single line and a differential pair of two cases. Therefore, the line width and line distance of the test coupon are the same as those of the line to be controlled. The most important thing is to measure the location of the site. In order to reduce the inductance of ground lead, TDR probe ground areas are usually very close to the local signal (probe tip), so test coupon measurement signal to ground distance and approach to meet the probe.

In the high-speed PCB design, the blank areas of the signal layer can be deposited with copper. How should the copper layers in the multiple signal layers be allocated on the ground and the power supply?

Most of the copper deposited in the blank area is grounded. Only when the copper is deposited near the high speed signal line, the distance between the deposited copper and the signal wire should be paid attention to, because the copper deposited will reduce the characteristic impedance of the wire. Also be careful not to affect the characteristic impedance of its layer, for example, in the structure of the dual strip line.

Is it possible to use the microstrip model to calculate the characteristic impedance of the signal line above the power plane? Can the signal between the power and ground planes be computed using a stripline model?

Yes, when calculating the characteristic impedance, the power plane and the ground plane must be regarded as the reference plane. For example, four layers: top layer, power layer, stratum bottom layer, and then the top line characteristic impedance model is a microstrip line model with power plane as reference plane.

Can automatic test points be generated through software on a high density printed circuit board, and can it meet the testing requirements for mass production in general?

The general software automatically generates test points to meet the test requirements. It is necessary to see whether the specifications of the additional test points meet the requirements of the test tools. In addition, if the line is too dense and the testing point is more strict, then it is impossible to automatically add test points to each line. Of course, you need to manually fill the place you want to test.

Does the addition of test points affect the quality of high-speed signals?

As for the quality of the signal, it depends on how fast the test point is added and how fast the signal is. Basically, additional test points (via or, DIP, pin), when tested, may be added to the line or pulled out a little line from the line. The former is equivalent to adding a small capacitor on the line, while the latter is more than one branch. These two cases will have some impact on the high-speed signal more or less, the extent of the impact is related to the signal frequency, speed and signal margin change rate (edge rate). The size of the effect can be learned by simulation. In principle, the smaller the test point, the better (of course, to meet the requirements of the test machine), the shorter the branch, the better.

How should the ground wires between the boards be connected to a number of PCB systems?

Each PCB board connected signal or power in the action, such as the A board has the power or signal is sent to the B board, the current must be equal from the formation to flow back to the A board (the Kirchoff current law). The current on this layer will flow back where the impedance is least. Therefore, in each power or signal interface, the number of pins allocated to the formation can not be too small to reduce the impedance, which can reduce the noise on the formation. In addition, can also analyze the current loop, especially the larger part of the current adjustment, the formation or wire connecting method, to control the current law (for example, somewhere in the low impedance, make the most of the current from the place to go), to reduce the influence of other sensitive signal.

Two characteristic impedance formulae that are often used

Microstrip line Z={87/[sqrt (Er+1.41)]}ln[5.98H/ (0.8W+T)] the W is linewidth, T is copper wire thickness, H is the reference plane distance of line, Er is the dielectric constant of PCB plate material. This formula must be applied only when 0.1< (W/H) <2.0, and 1< (Er) <15 are applied.

Stripline Z=[60/sqrt (Er)]ln{4H/[0.67 PI (T+0.8W)]} the H is distance of two reference plane, The line be routed at amid the two reference plane. This formula must be applied in the case of W/H<0.35 and T/H<0.25.

Whether can add a ground line to a differential signal line?

The middle of a differential signal is usually not ground. Because of the application principle of differential signals, the most important point is the advantage of differential signal inter coupling, such as flux, cancellation,noise immunity noise capability and so on. If the ground wire is in the middle, it will destroy the coupling effect

The principle of PCB and the point of the enclosure ground

The principle of selecting the PCB and the shell site selection is to provide a low impedance path using the chassis ground to return current and to control the path of this return current. For example, usually in the vicinity of high frequency devices or clock generator, can be fixed with screws by PCB ground and chassis formation are connected to minimize the current loop area, also is to reduce electromagnetic radiation

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